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Cache memory
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#	Item
581	Prof. Dr.-Ing. Dr. h. c. mult. P. J. Kühn Prof. Dr.-Ing. Dr. h. c. mult. P. J. Kühn International Symposium on Memory Management June 10–11, 2006 Ottawa, Canada Add to Reading List Source URL: www.cs.technion.ac.il Language: English - Date: 2010-02-20 10:44:16 Computing Pointer Garbage collection Classic RISC pipeline Microarchitecture Processor register CPU cache Instruction set Memory barrier Computer hardware Computer architecture Central processing unit
582	DECchip[removed]Evaluation Board User’s Guide Order Number: EC–N0351–72 Revision/Update Information: Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:02:08 Alpha 21064 Dynamic random-access memory DEC Alpha Computer workstations SIMM CPU cache DEC 4000 AXP DEC 7000/10000 AXP Computer hardware Computing Computer memory
583	Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation ˜ ´ Garzar´an, Milos Prvulovic, V´ıctor Vinals Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2003-09-29 23:57:21 Central processing unit Computer memory CPU cache Cache Parallel computing Hazard Superscalar Stack Computing Computer hardware Computer architecture
584	IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING (TDSC) 1 Using Register Lifetime Predictions to Protect Register Files Against Soft Errors Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-08-29 19:16:16 Central processing unit Computer memory Register renaming CPU cache Register file Branch predictor Parity bit Processor register 64-bit Computer architecture Computer hardware Computing
585	CAVA: Using Checkpoint-Assisted Value Prediction to Hide L2 Misses LUIS CEZE, KARIN STRAUSS, JAMES TUCK, and JOSEP TORRELLAS University of Illinois at Urbana–Champaign and JOSE RENAU Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 00:10:17 Central processing unit Computer memory Runahead Cache CPU cache Branch predictor Microarchitecture Memory hierarchy Speculative execution Computer architecture Computer hardware Computer engineering
586	BulkSC: Bulk Enforcement of Sequential Consistency Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2007-04-07 18:09:31 Computer architecture Central processing unit CPU cache Cache Parallel computing C dynamic memory allocation Microarchitecture Advanced Micro Devices Transactional memory Computer hardware Computer memory Computing
587	Design Note: Target Considerations for Coldfire † Jonathan S. Shapiro, Ph.D. The EROS Group, LLC Dec 1, 2007 Abstract Add to Reading List Source URL: www.coyotos.org Language: English - Date: 2014-08-13 02:10:11 Virtual memory Computing Computer memory CPU cache Cache Page table Page Microkernel Kernel Computer architecture Central processing unit Computer hardware
588	Scalable Cache Miss Handling for High Memory-Level Parallelism Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-10-02 23:12:53 Central processing unit Microprocessors Computer memory CPU cache Cache Runahead Multi-core processor Microarchitecture Memory-level parallelism Computer hardware Computer architecture Computing
589	BulkCommit: Scalable and Fast Commit of Atomic Blocks in a Lazy Multiprocessor Environment Xuehai Qian, Benjamin Sahelices Josep Torrellas, Depei Qian Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-02-19 00:20:13 Cache Central processing unit Computer memory C dynamic memory allocation Computer architecture Computer hardware Computing CPU cache
590	Volition: Scalable and Precise Sequential Consistency Violation Detection Xuehai Qian, Josep Torrellas Benjamin Sahelices Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-01-25 16:44:41 Cache Central processing unit Parallel computing Computing Volition Computer memory Computer hardware CPU cache

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